The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same and, more particularly, to a technique which is particularly effective when applied to a semiconductor integrated circuit device having an SRAM (Static Random Access Memory).
A memory cell of an SRAM or a semiconductor memory device is composed of: a flip-flop circuit acting as an information storage unit for storing information of 1 bit; and a pair of transfer MISFETs (Metal Insulator Semiconductor Field Effect Transistors) for controlling the electrical connection between writing/reading data lines and the flip-flop circuit.
The flip-flop circuit of the memory cell is composed of a pair of CMOS (Complementary Metal Oxide Semiconductor) inverters, for example. Each of these CMOS inverters is composed of one drive MISFET and one load MISFET. In this case, the memory cell is of a complete CMOS type of a combination of two drive MISFETs, two load MISFETs and two transfer MISFETs. Of these MISFETs, the transfer MISFETs and the drive MISFETs are of n-channel type whereas the load MISFETs are of p-channel type.
A pair of input/output terminals of the flip-flop circuit (the CMOS inverter) are cross-connected through a pair of wiring lines called xe2x80x9clocal wiring linesxe2x80x9d, for example. Moreover, one of these input/output terminals is supplied with a power supply voltage (e.g., 3 V) of a circuit through a power supply voltage line whereas the other is supplied with a reference voltage (e.g., 0 V) of the circuit through a reference voltage line.
In U.S. Pat. No. 5,523,598, issued Jun. 4, 1996, there is disclosed an SRAM of the complete CMOS type, which is equipped with a pair of aforementioned local wiring lines. In this SRAM, the gate electrodes of the six MISFETs constituting the memory cells, the power supply voltage line connected with one input/output terminal of the flip-flop circuit, the reference voltage line connected with the other input/output terminal, the pair of local wiring lines, and the data lines connected with the drain regions of the transfer MISFETs are individually provided in different conductive layers. In this SRAM, moreover, the local wiring lines and other conductive layers (e.g., the reference voltage line) are arranged to intersect each other so that the reduction in the alpha particle soft error resistance, which might occur upon the miniaturization of the memory cell size and the lowering of the operating power supply voltage, is prevented by forming a capacitor element in the intersection region to increase the storage node capacitance of the memory cells.
Various problems arise in connection with the SRAM disclosed in U.S. Pat. No. 5,523,598. In the SRAM disclosed the reference voltage line, and the data lines are formed in different conductive layers. As a result, the mask registration allowance when forming the connection holes in the interlayer insulating film by using a photoresist as the mask is increased, resulting in increase of the memory cell size. When the gate electrodes are formed of a conductive film of a first layer, the local wiring lines are formed of a conductive film of a second layer, and the power supply lines are formed of a conductive film of a third layer, for example, it is necessary to ensure the registration allowance for both the gate electrodes and the local wiring lines.
In the SRAM disclosed in the aforementioned U.S. Pat. No. 5,523,598, the paired local wiring lines are formed of the same conductive film. This makes it necessary to arrange the two local wiring lines transversely in the memory cell, so that the memory cell size is increased.
An object of the present invention is to provide a semiconductor integrated circuit device (for example, a semiconductor memory such as a complete CMOS SRAM) having a reduced memory cell size, and a method of fabricating such semiconductor device.
Another object of the present invention is to provide a semiconductor integrated circuit device (e.g., semiconductor memory such as a complete CMOS SRAM) having improved alpha particle soft error resistance, and a method of fabricating such semiconductor device. particle soft error resistance, and a method of fabricating such semiconductor device.
The aforementioned and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
Illustrations of the invention to be disclosed herein will be briefly described in the following. These illustrations are representative of the present invention and do not define the scope thereof, the scope being defined by the appended claims.
According to the present invention, there is provided a semiconductor integrated circuit device comprising an SRAM including memory cells having a flip-flop circuit composed of a pair of drive MISFETs and a pair of load MISFETs, and having a pair of transfer MISFETs, which device is constructed such that the individual gate electrodes of the drive MISFETs, the load MISFETs and the transfer MISFETs are composed of a first conductive film formed over a major face of a semiconductor substrate; one of the local wiring lines cross-connecting a pair of input/output terminals of the flip-flop circuit, is composed of a second conductive film formed over that first conductive film; and the other of the local wiring lines is composed of a third conductive film formed over the second conductive film, and a method of fabricating the device.
The semiconductor integrated circuit device of the present invention is constructed such that the one and the other of the local wiring lines are so arranged as to have at least partially and vertically overlapping portions, and the one and the other of the local wiring lines and an insulating film interposed therebetween constitute a capacitor element.
In regard to a method for manufacturing a semiconductor integrated circuit device, there is provided a method for manufacturing a semiconductor integrated circuit device (e.g., an SRAM) containing memory cells each having a flip-flop circuit including a pair of drive MISFETs and a pair of load MISFETs, and a pair of transfer MISFETs, comprising the steps of:
(a) preparing (e.g., providing) a semiconductor substrate having a major face, over which the individual gate electrodes of the drive MISFETs, the load MISFETs and the transfer MISFETs are formed;
(b) forming a pair of local wiring lines cross-connecting a pair of input/output terminals of the flip-flop circuit, over the gate electrodes;
(c) forming side wall spacers on the individual side walls of the gate electrodes and the local wiring lines; and
(d) forming connection holes reaching the source regions of the drive MISFETs or the load MISFETs by depositing a second insulating film of an etching rate different from (e.g., greater than) that of the first insulating film over the local wiring lines, on which the side wall spacers are formed, and by etching the second insulating film. Also provided is the device fabricated by this method.
In regard to a method for manufacturing a semiconductor integrated circuit device, there is also provided a method for manufacturing a semiconductor integrated circuit device (e.g., an SRAM) containing memory cells each having a flip-flop circuit composed of a pair of drive MISFETs and a pair of load MISFETs, and a pair of transfer MISFETs, comprising the steps of:
(a) preparing (e.g., providing) a semiconductor substrate having a major face, over which the individual gate electrodes of the drive MISFETs, the load MISFETs and the transfer MISFETs are formed;
(b) forming one of a pair of local wiring lines cross-connecting a pair of input/output terminals of the flip-flop circuit, over the gate electrodes;
(c) forming the other of the paired local wiring lines over the local wiring line formed in step (d);
(d) forming side wall spacers on the individual side walls of the gate electrodes and the one and the other of the local wiring lines, by etching a first insulating film which is deposited over the other of the local wiring lines; and
(e) forming connection holes reaching the source regions of the drive MISFETs or the load MISFETs by depositing a second insulating film of an etching rate different from that of the first insulating film over the other of the local wiring lines, on which the side wall spacers are formed, and by etching the second insulating film. Also provided is the device fabricating by this method.
According to the means thus far described, the paired local wiring lines cross-connecting the input/output terminals of the flip-flop circuit of the memory cell are formed in different conductive layers vertically with respect to the substrate. Therefore the space, required when the paired local wiring lines are composed of the same conductive film, for arranging the two local wiring lines transversely, can be eliminated, and the local wiring lines can be arranged partially in an overlapping manner, thereby reducing the area occupied by the memory cell.
According to the means thus far described, the one and the other of the local wiring lines are so arranged as to overlap vertically, and a capacitor element is formed of the one and the other of the local wiring lines and an insulating film interposed therebetween, so that the storage node capacitance of the memory cell can be increased, preventing the lowering of alpha particle soft error resistance entailed by the miniaturization of the memory cell size and the lowering of the operation power supply voltage. For example, the capacitor area can be about half the area of the memory cell, which realizes a thick capacitor dielectric. Soft error immunity can be achieved even at a 1.8 V supply voltage.
According to the means thus far described, the mask registration allowance when the connection holes are formed in the interlayer insulating film by using a photoresist as the mask can be eliminated, reducing the area occupied by the memory cells. The connection holes can be formed by a self-alignment technique (self-aligned to both the gates and the local wiring lines).